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MC74HC541A Octal 3-State Noninverting Buffer/Line Driver/Line Receiver
High-Performance Silicon-Gate CMOS
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The MC74HC541A is identical in pinout to the LS541. The device inputs are compatible with Standard CMOS outputs. External pull-up resistors make them compatible with LSTTL outputs. The HC541A is an octal noninverting buffer/line driver/line receiver designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. This device features inputs and outputs on opposite sides of the package and two ANDed active-low output enables. The HC541A is similar in function to the HC540A, which has inverting outputs.
Features
MARKING DIAGRAMS
20 PDIP-20 N SUFFIX CASE 738 1 1 20 20 1 SOIC-20 DW SUFFIX CASE 751D 1 74HC541A AWLYYWWG MC74HC541AN AWLYYWWG
20
* * * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent Gates Pb-Free Packages are Available*
20 20 1 TSSOP-20 DT SUFFIX CASE 948E 1 HC 541A ALYWG G
20 1
20 SOEIAJ-20 F SUFFIX CASE 967 1
74HC541A AWLYWWG
A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G = Pb-Free Package G = Pb-Free Package (Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2005
1
July, 2005 - Rev. 4
Publication Order Number: MC74HC541A/D
MC74HC541A
VCC OE2 20 19 Y1 18 Y2 17 Y3 16 Y4 15 Y5 14 Y6 13 Y7 12 Y8 11 OE1 L L H X
FUNCTION TABLE
Inputs OE2 L L X H A L H X X L H Z Z Output Y
1 OE1
2 A1
3 A2
4 A3
5 A4
6 A5
7 A6
8 A7
9 A8
10 GND
Figure 1. Pinout: 20-Lead Packages (Top View)
X = Don't Care Z = High Impedance
A1 A2 A3 Data Inputs A4 A5 A6 A7 A8
2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Noninverting Outputs
Output OE1 1 Enables OE2 19
PIN 20 = VCC PIN 10 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Device MC74HC541AN MC74HC541ANG MC74HC541ADW MC74HC541ADWG MC74HC541ADWR2 MC74HC541ADWR2G MC74HC541ADT MC74HC541ADTG MC74HC541ADTR2 MC74HC541ADTR2G MC74HC541AF MC74HC541AFG MC74HC541AFEL MC74HC541AFELG Package PDIP-20 PDIP-20 (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) SOIC-20 WIDE SOIC-20 WIDE (Pb-Free) TSSOP-20* TSSOP-20* TSSOP-20* TSSOP-20* SOEIAJ-20 SOEIAJ-20 (Pb-Free) SOEIAJ-20 SOEIAJ-20 (Pb-Free) Shipping 18 Units / Rail 18 Units / Rail 38 Units / Rail 38 Units / Rail 1000 Tape & Reel 1000 Tape & Reel 75 Units / Rail 75 Units / Rail 2500 Tape & Reel 2500 Tape & Reel 40 Units / Rail 40 Units / Rail 2000 Tape & Reel 2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free.
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MC74HC541A
MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG TL TJ qJA DC Supply Voltage DC Input Voltage DC Output Voltage (Note 1) DC Input Diode Current DC Output Diode Current DC Output Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Range Lead Temperature, 1 mm from Case for 10 Seconds Junction Temperature under Bias Thermal Resistance PDIP SOIC TSSOP PDIP SOIC TSSOP Parameter Value *0.5 to )7.0 *0.5 v VI v )0.5 *0.5 v VO v )0.5 $20 $35 $35 $75 $75 *65 to )150 260 )150 67 96 128 750 500 450 Level 1 Oxygen Index: 30% - 35% Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) Above VCC and Below GND at 85_C (Note 5) UL 94 V-0 @ 0.125 in > 4000 > 300 > 1000 $300 V Unit V V V mA mA mA mA mA _C _C _C _C/W
PD
Power Dissipation in Still Air at 85_C
mW
MSL FR VESD
Moisture Sensitivity Flammability Rating ESD Withstand Voltage
ILatchup 1. 2. 3. 4. 5. 6.
Latchup Performance
mA
IO absolute maximum rating must be observed. Tested to EIA/JESD22-A114-A. Tested to EIA/JESD22-A115-A. Tested to JESD22-C101-A. Tested to EIA/JESD78. For high frequency or heavy load considerations, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC DC Supply Voltage Parameter (Referenced to GND) Min 2.0 0 Max 6.0 Unit V V
IIIIIIIIII II I II I IIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIII II I I I I IIIIIIIIIIIIIIIIIIIIIIII III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I
VIN, VOUT TA DC Input Voltage, Output Voltage (Referenced to GND) VCC Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 3) *55 0 0 0 )125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 7. Unused inputs may not be left open. All inputs must be tied to a high-logic voltage level or a low-logic input voltage level.
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MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit Symbol VIH Parameter Minimum High-Level Input Voltage Condition VOUT = 0.1 V |IOUT| 20 mA VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 4.5 6.0 |IOUT| 3.6 mA |IOUT| 6.0 mA |IOUT| 7.8 mA 3.0 4.5 6.0 2.0 4.5 6.0 |IOUT| 3.6 mA |IOUT| 6.0 mA |IOUT| 7.8 mA 3.0 4.5 6.0 6.0 6.0 *55 to 25_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.48 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.26 $0.1 $0.5 v85_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.34 3.84 5.34 0.1 0.1 0.1 0.33 0.33 0.33 $1.0 $5.0 v125_C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 1.9 4.4 5.9 2.20 3.70 5.20 0.1 0.1 0.1 0.40 0.40 0.40 $1.0 $10.0 mA mA V Unit V
VIL
Maximum Low-Level Input Voltage
VOUT = VCC - 0.1 V |IOUT| 20 mA
V
VOH
Minimum High-Level Output Voltage
VIN = VIL |IOUT| 20 mA VIN = VIL
V
VOL
Maximum Low-Level Output Voltage
VIN = VIH |IOUT| 20 mA VIN = VIH
IIN IOZ
Maximum Input Leakage Current Maximum 3-State Leakage Current
VIN = VCC or GND Output in High Impedance State VIN = VIL or VIH VOUT = VCC or GND VIN = VCC or GND IOUT = 0 mA
ICC
Maximum Quiescent Supply Current (per Package)
6.0
4
40
160
mA
8. Information on typical parametric values can be found in the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input A to Output Y (Figures 3 and 5) VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 *55 to 25_C 80 30 18 15 110 45 25 21 110 45 25 21 60 22 12 10 10 15 v85_C 100 40 23 20 140 60 31 26 140 60 31 26 75 28 15 13 10 15 v125_C 120 55 28 25 165 75 38 31 165 75 38 31 90 34 18 15 10 15 Unit ns
tPLZ, tPHZ
Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6)
ns
tPZL, tPZH
Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 6)
ns
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 3 and 5)
ns
CIN COUT
Maximum Input Capacitance Maximum 3-State Output Capacitance (High Impedance State Output)
pF pF
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V, VEE = 0 V CPD Power Dissipation Capacitance (Per Buffer) (Note 10)
2f
35
pF
10. Used to determine the no-load dynamic power consumption: PD = CPD VCC Semiconductor High-Speed CMOS Data Book (DL129/D).
+ ICC VCC . For load considerations, see the ON
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MC74HC541A
tr 90% INPUT A tPLH 90% OUTPUT Y 50% 10% tTLH tTHL 50% 10% tPHL GND tf VCC
Figure 3. Switching Waveform
VCC OE1 or OE2 tPZL OUTPUT Y 50% 10% tPZH OUTPUT Y 50% HIGH IMPEDANCE tPHZ 90% VOH VOL 50% tPLZ 50% GND HIGH IMPEDANCE
Figure 4. Switching Waveform
TEST POINT OUTPUT DEVICE UNDER TEST CL *
*Includes all probe and jig capacitance
Figure 5. Test Circuit
TEST POINT OUTPUT DEVICE UNDER TEST 1 kW CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.
CL *
*Includes all probe and jig capacitance
Figure 6. Test Circuit
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MC74HC541A
PIN DESCRIPTIONS
INPUTS A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8, 9)
Data input pins. Data on these pins appear in non-inverted form on the corresponding Y outputs, when the outputs are enabled.
CONTROLS OE1, OE2 (PINS 1, 19)
device functions as an non-inverting buffer. When a high voltage is applied to either input, the outputs assume the high impedance state.
OUTPUTS Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14, 13, 12, 11)
Output enables (active-low). When a low voltage is applied to both of these pins, the outputs are enabled and the
Device outputs. Depending upon the state of the output enable pins, these outputs are either non-inverting outputs or high-impedance outputs.
To 7 Other Buffers
One of Eight Buffers INPUT A
VCC
OUTPUT Y
OE1 OE2
Figure 7. Logic Detail
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MC74HC541A
PACKAGE DIMENSIONS
PDIP-20 N SUFFIX PLASTIC DIP PACKAGE CASE 738-03 ISSUE E
-A-
20 1 11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040
MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
SOIC-20 DW SUFFIX CASE 751D-05 ISSUE G
D
A
11 X 45 _
q
H
M
B
M
20
10X
0.25
E
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
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L
MC74HC541A
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX CASE 948E-02 ISSUE B
K REF
M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
20X
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
B L
PIN 1 IDENT 1 10
J J1
-U-
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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IIII IIII IIII
SECTION N-N M DETAIL E
20
11
K K1
0.25 (0.010)
-W-
DIM A B C D F G H J J1 K K1 L M
MC74HC541A
PACKAGE DIMENSIONS
SOEIAJ-20 F SUFFIX CASE 967-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 12.35 12.80 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 0.81 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.486 0.504 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.032
20
11
LE Q1 M_ L DETAIL P
E HE
1
10
Z D e VIEW P A
c
b 0.13 (0.005)
M
A1 0.10 (0.004)
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MC74HC541A
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74HC541A/D

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